Communications between data processing systems have become more complex with the increased capability of individual data processing units. This communication capability is commonly termed networking. The specific area of interest for this invention is a single information bus connected to several processor units and several peripheral units. Traditionally, one processor unit is programmed to regulate the communications over the bus between the processing units and the peripheral units. In network terminology the communications controlling processor is termed the bus master and the remaining communication units termed slaves. In such a networking arrangement only the bus master may initiate any communications transactions on the bus. The slave units are only allowed to respond to communications from the bus master. A variation of this type of network provides for the bus master responsibility to be transferred among the processing units. In this manner any processor may address a peripheral device. If two processors desire to be bus master at the same time, a collision can occur on the information bus. Therefore, arbitration circuitry is provided to designate one of the communication bus requesting processors as the bus master.
An example of the above data processing system is disclosed in U.S. Pat. No. 3,997,896, entitle "Data Processing System Providing Split Bus Cycle Operation", which discloses a data processing system including a common bus and several units connected to transfer information asynchronously, wherein logic is provided for enabling a split bus cycle operation where a bus master unit requesting information from a slave during a first bus cycle may receive that information from the slave during a later bus cycle. This slave, at the later bus cycle requests that the bus arbiter designate the slave as bus master in order that the slave may provide that information to the original bus master. Further disclosures of this type of bus architecture are contained in U.S. Pat. No. 4,181,974, entitled "System Providing Multiple Outstanding Information Request" and U.S. Pat. No. 4,236,203, entitled "System Providing Multiple Fetch Bus Cycle Operation".
In each of the above patents, the slave device is required to become bus master at the time the information that was originally requested becomes available. However, some slave devices do not include the capability to function as a bus master. Therefore, it is an object of the present invention to provide a data processing system including a communications bus that enables a slave that cannot become bus master to provide requested information during later bus cycles.